1. Field of the Invention
The present invention relates generally to arithmetic circuits for digital signal processors and more particularly to an array multiplier for computing the product of two operands.
2. Relevant Background
Portable electronic devices have become ubiquitous to modem life. Two relentless trends in portable electronic devices are increased functionality and decreased size. Increased functionality demands require increased computing capability—in particular, ever faster and more powerful processors. Decreased size requires decreasing the size of batteries used to power the processor and other electronics in the device. Therefore, manufacturers are faced with the seemingly contradictory goals of increasing computing capability, and hence power requirements, while at the same time decreasing battery size. While improvements in battery technology partially offset the problem, the decreasing size of batteries and demands for more computing capability impose a strict power budget on all portable electronic device electronics, and in particular on the processor.
The multiplier is a core component of many digital signal processors. The array multiplier is a popular architecture due to its relatively simple and regular structure. However, array multipliers have some drawbacks compared to other multiplier architectures, namely in terms of latency and power consumption. In array multipliers, results take time to propagate through the array. The propagation of the results through the array causes transistors in the array to switch multiple times before settling on final value. This switching activity is the primary cause of power dissipation in array multipliers.